Annular gate and technique for fabricating an annular gate

ABSTRACT

A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to integrated circuits and, moreparticularly, to integrated circuits implementing vertical transistorshaving annular gate structures.

2. Description of the Related Art

This section is intended to introduce the reader to various aspects ofart that may be related to various aspects of the present invention,which are described and/or claimed below. This discussion is believed tobe helpful in providing the reader with background information tofacilitate a better understanding of the various aspects of the presentinvention. Accordingly, it should be understood that these statementsare to be read in this light, and not as admissions of prior art.

Semiconductor memory devices, such as dynamic random access memory(DRAM) devices, are widely used for storing data in systems such ascomputer systems. A DRAM memory cell typically includes an access devicesuch as a field effect transistor (FET) coupled to a storage device suchas a capacitor. The access device allows the transfer of charges to andfrom the storage capacitor thereby facilitating read and writeoperations in the memory device. The memory cells are typically arrangedin a number of rows and columns to provide a memory array.

With the constantly increasing demand for higher data storage capacity,memory arrays are becoming more dense. Memory density is typicallylimited by current processing technologies used for fabrication of thememory arrays. One technique for providing higher density memory arraysis to incorporate vertical technology in fabricating the accesstransistors. Among the concerns in fabricating memory devices is toprovide memory cells with minimal leakage to prevent the loss of storagecell data. Further, alpha-particle induced soft errors which alter thedata stored in the memory cells should also be considered, andsimplification in fabrication techniques may also be desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

Advantages of the invention may become apparent upon reading thefollowing detailed description and upon reference to the drawings inwhich:

FIG. 1 illustrates a partial exemplary schematic illustration of anintegrated circuit incorporating an array of memory cells that may befabricated in accordance with the techniques described herein;

FIG. 2-9 illustrate a technique for fabricating an access device in amemory cell in accordance with the present invention;

FIG. 10 illustrates a cross-sectional view of the exemplary accessdevice illustrated in FIG. 9 further incorporating an exemplary storagedevice;

FIG. 11 illustrates a cross-sectional view of an alternate embodiment ofa bitline fabricated in accordance with the present techniques;

FIGS. 12 and 13 illustrate cross-sectional views of an alternateembodiment of a wordline fabricated in accordance with the presenttechniques;

FIGS. 14 and 15 illustrate cross-sectional views of another embodimentof a wordline fabricated in accordance with the present techniques;

FIGS. 16-18 illustrate an exemplary gate structure fabricated inaccordance with the present techniques; and

FIGS. 19 and 20 illustrate an alternate exemplary gate structurefabricated in accordance with the present techniques.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present invention will bedescribed below. In an effort to provide a concise description of theseembodiments, not all features of an actual implementation are describedin the specification. It should be appreciated that in the developmentof any such actual implementation, as in any engineering or designproject, numerous implementation-specific decisions must be made toachieve the developers' specific goals, such as compliance withsystem-related and business-related constraints, which may vary from oneimplementation to another. Moreover, it should be appreciated that sucha development effort might be complex and time consuming, but wouldnevertheless be a routine undertaking of design, fabrication, andmanufacture for those of ordinary skill having the benefit of thisdisclosure.

FIG. 1 is a partial exemplary schematic illustration of an integratedcircuit, such as a memory device 10, incorporating an array of memorycells which may be fabricated in accordance with the techniquesdescribed herein. The memory device 10 may be, for example, a dynamicrandom access memory (DRAM) device. In the exemplary embodiment, thememory device 10 includes a number of memory cells 12 arranged in a gridpattern comprising a number of rows and columns. As can be appreciated,the number of memory cells (and corresponding rows and columns) may varydepending on system requirements and fabrication technology.

Each memory cell 12 includes an access device and a storage device aspreviously discussed. In the present exemplary embodiment, the accessdevice comprises a field-effect transistor (FET) 14 and the storagedevice comprises a capacitor 16. The access device is implemented toprovide controlled access to the storage device. In the exemplary memorycell 12, the FET 14 includes a drain terminal 18 and a source terminal20, along with a gate terminal 22 for controlling conduction between thedrain and source terminals 18, 20. The storage device, such as thecapacitor 16, is coupled to one of the source/drain terminals 18, 20.The terminal of the capacitor 16 that is not coupled to the FET 14 maybe coupled to a reference plane.

It should be noted that although the above description depicts theterminal of the access device that is coupled to the capacitor 16 as thesource 20 and the other non-gate terminal of the access device as thedrain 18, during read and write operations, the FET 14 may be operatedsuch that each of the terminals 18 and 20 operates at one time oranother as a source or a drain. Accordingly, for purposes of furtherdiscussion, it should be recognized that whenever a terminal isidentified as a source or a drain, it is only for convenience. Duringoperation of the FET 14 either terminal could be a source or a draindepending on the manner in which the FET 14 is being controlled by thevoltages applied to the terminals 18, 20, and 22 of the FET 14.

As previously described, the memory array is arranged in a series ofrows and columns. To implement the data storage capabilities in thememory cell 12, an electrical charge is placed on the drain 18 of theFET 14 via a bitline (BL). By controlling the voltage at the gate 22 viathe wordline (WL), a voltage potential may be created across the FET 14such that the electrical charge at the drain 18 can flow to thecapacitor 16. As can be appreciated, by storing an electrical charge inthe capacitor 16, the charge may be interpreted as a binary data valuein the memory cell 12. For instance, for a single-bit storage device, apositive charge above a known threshold voltage may be interpreted as abinary “1.” If the charge in the capacitor 16 is below the thresholdvalue, a binary value of “0” is said to be stored in the memory cell 12.

As previously described, the bitlines BL are used to read and write datato and from the memory cells 12. The wordlines WL are used to activatethe FET 14 to access a particular row of a memory cell 12. Accordingly,the memory device 10 includes an address buffer 24, row decoder 26, andcolumn decoder 28. As can be appreciated, the address buffer 24 controlseach of the row decoder 26 and the column decoder 28. The row decoder 26and column decoder 28 selectively access the memory cells 12 in responseto address signals that are provided on the address bus 30 during read,write, and refresh operations. The address signals are typicallyprovided by an external controller such as a microprocessor or othermemory controller. The column decoder 28 may also include senseamplifiers and input/output circuitry to farther enable data to be readto and from the memory cell 12 via the bitlines BL.

In one exemplary mode of operation, the memory device 10 receives anaddress of a particular memory cell 12 at the address buffer 24. Theaddress buffer 24 identifies one of the wordlines WL of the particularmemory cell 12 corresponding to the requested address and passes theaddress to the row decoder 26. The row decoder 26 selectively activatesthe particular wordline WL to activate the FETs 14 of each memory cell12 that is connected to the selected wordline WL. The column decoder 28selects the bitline (or bitlines) BL of the memory cell 12 correspondingto the requested address. For a write operation, data received byinput/output circuitry is coupled to the selected bitline (or bitlines)BL and provides for the charge or discharge of the capacitor 16 of theselected memory cell 12 through the FET 14. The charge corresponds tobinary data, as previously described. For a read operation, data storedin the selected memory cell 12, represented by the charge stored in thecapacitor 16, is coupled to the selected bitline (or bitlines) BL,amplified by the sense amplifier, and a corresponding voltage level isprovided to the input/output circuit in the column decoder 28.

As can be appreciated, the memory array described with reference to FIG.1 of the memory device 10 may be fabricated through a variety oftechnologies. One particularly advantageous technique for fabricatingthe memory cells 12 will now be described with reference to FIGS. 2-10.The advantages of the presently described fabrication techniques willbecome apparent upon reading the following detailed description withreference to FIGS. 2-10. To provide a high density memory device 10,vertical transistor technology wherein the channel of the FET 14 isfabricated perpendicular to the surface of a wafer rather than parallelto the surface, is implemented as further described below.Advantageously, the vertically oriented access FET 14 may occupy lessspace than other techniques. Further, by incorporating verticallyoriented access FETs 14, the memory cells 12 are less susceptible toalpha-radiation.

FIG. 2 illustrates a semiconductor substrate material such as silicon(Si). More specifically, the substrate 32 may comprise a P-dopedsilicon. To fabricate the vertically oriented access FETs 14, thesubstrate 32 is subtractively etched to produce silicon pillars 33. Asdescribed further below, the pillars 33 will eventually form thechannels of the FETs 14. The pillars 33 may be formed through any one ofa number of commonly known etching techniques, such as plasma etching,ion beam etching, or reactive ion etching (RIE). Each pillar 33 may havea height of approximately 2.0 microns and a diameter of 0.2 microns, forexample. In the present embodiment, each pillar 33 may be generallycylindrical such that the top view of each pillar 33 is generallycircular. This shape will facilitate the eventual fabrication of annularrings around the pillars 33, as described further below. Alternatively,pillars having other geometric cross-sectional shapes, such asrectangles, squares, or ellipses for example, may be implemented toconstruct the channel of the FET 14 such that the structure may besurrounded by other layers in the fabrication of the FET 14. As can beappreciated, the specific heights and thicknesses of the features andmaterials described herein are exemplary in nature and are meant forpurposes of illustration only. Accordingly, the exemplary dimensionsprovided herein are in no way meant to limit the scope of the presenttechniques. Further, while the present exemplary embodiment illustratespillars 33 that are perpendicular to the surface of the substrate 32,the pillars 33 may extend away from the surface of the substrate 32 atan angle. For instance, in an alternate embodiment, the pillars 33 maybe fabricated at an angle in the range of 45° to 90° with respect to thesurface of the substrate 32.

After formation of the pillars 33, an insulation layer such as an oxidelayer 34 is applied on top of a substrate 32 as illustrated in FIG. 3.The insulation layer may comprise any number of non-conductive materialssuch as oxide, silicon dioxide, silicon nitride, etc. The oxide layer 34is applied by chemical vapor deposition (CVD), for example. The oxidelayer 34 may be disposed at a thickness of approximately 0.2 microns,for example. As can be appreciated by those skilled in the art, theoxide layer 34 is disposed over the entire surface of the substrate 32.As can be appreciated, a described, the silicon pillar 33 also includesn+ contact regions 38 which may be formed by out diffusion from thepolysilicon layer 36. The advantages of the annular ring pattern aroundthe silicon pillars 33 used to form the bitline polysilicon layer 36will become more apparent through the subsequent discussion herein.

After deposition of the polysilicon layer 36 and the formation of the n+contact regions 38, another isolation layer, such as an oxide layer 40,is disposed on the polysilicon layer 36 as illustrated in FIG. 6. As canbe appreciated, the oxide layer 40 electrically isolates the polysiliconlayer 36 from layers subsequently disposed over the oxide layer 40. Aswith the oxide layer 34, the oxide layer 40 is deposited, patterned andetched to provide a structure as illustrated in FIG. 6. The thickness ofthe oxide may be 0.2 microns, for example. FIG. 6 further illustrates athin gate oxide layer 42 which is disposed or grown around the pillar 33to facilitate the functionality of the gate 22 (FIG. 1) of the FET 14.The gate oxide layer 42 may be grown to a thickness of approximately 60angstroms by any one of a number of conventional means. It should benoted that for purposes of etch selectivity, the oxide layer 40 and thegate oxide 42 may comprise different insulated materials with respect toone another, such as oxide, silicon dioxide, silicon nitride, TEOS, etc.

After deposition of the oxide layer 40 and the growth of the gate oxidelayer 42, another layer of polysilicon is disposed, patterned, andetched to form the wordline polysilicon layer 44, as illustrated in FIG.7. The thickness of the wordline polysilicon layer 44 extending upwardlyfrom the surface of the substrate 32 in the direction of the pillar 33may be about 0.8 microns, for example. The thickness of the wordlinepolysilicon layer 44 extending outwardly from the surface of the pillar33 may be about 0.1 to about 0.2 microns, for example. In thecross-section illustrated with reference to FIG. 7, the wordlinepolysilicon layer 44 appears to provide a gate region on either side ofthe pillar 33. However, as can be appreciated, the wordline polysiliconlayer 44 is patterned such that the polysilicon material completelysurrounds the pillar 33, as with the bitline polysilcon layer 36. Thewordline polysilicon layer 44 extends in a direction perpendicular tothe page. As illustrated in FIG. 8, the wordline polysilicon layer 44 ispatterned such that it runs perpendicular to the bitline polysiliconlayer 36. FIG. 8 illustrates a cross-sectional top view of the structureillustrated with reference to FIG. 7 and taken along cut lines 8-8. Theadvantages of the annular ring pattern around the silicon pillars 33used to form the wordline polysilicon layer 44 will become more apparentthrough the subsequent discussion herein.

After deposition, patterning, and etching of the wordline polysiliconlayer 44, a dielectric layer 46, such as silicon dioxide or siliconnitride, is deposited over the entire structure such that each of thepillars 33 are completely covered, as illustrated with reference to FIG.9. The dielectric layer 46 may be disposed by chemical vapor deposition(CVD), for example. Thus, the dielectric layer 46 may be deposited at athickness of more than 1.0 micron, in the present exemplary embodiment,such that the dielectric layer 46 is disposed to a height approximatelycoplanar with the height of the pillars 33.

After deposition of the dielectric layer 46, the surface of thestructure may be planarized such as by chemical-mechanicalpolishing/planarization (CMP). The surface of the structure isplanarized to a point where the thin gate oxide layer 42 is removed fromthe top of the pillar 33 thereby exposing the silicon pillar 33 below.Finally, an n+ contact region 48 is formed at the top of the pillar 33.The n+ contact region 48 may be formed through gas diffusion or ionimplant techniques, for example. The n+ contact region 48 forms thesource 20 of the FET 14 which will be coupled to the capacitor 16 formedin subsequent processing steps illustrated with respect to FIG. 10.

FIG. 9 illustrates the completed fabrication of the access device (FET14). As can be appreciated, the silicon pillar 33 thus forms a channelof the FET 14. By completely surrounding the channel with the wordlinepolysilicon layer 44, the gate 22 functions as a channel with increaseddrive capabilities over access devices having conventional gatestructures. Further, the present techniques also provide improvedrefresh of the memory cell 12 since there are no PN junctions of thecapacitor to the substrate, thereby reducing the leakage paths and thefrequency of the refresh. Finally, the annular structure of the bitlinepolysilicon layer 36 may offer further advantages of the presenttechniques, as well.

As previously described, to complete the memory cell 12, a storagedevice, such as a capacitor 16 is fabricated. As can be appreciated bythose skilled in the art, any number of capacitor types and fabricationtechniques may be used in conjunction with the FET structure describedabove with reference to FIGS. 2-9. FIG. 10 illustrates a completedmemory cell structure 12 incorporating an exemplary storage device. Inthe exemplary embodiment, a crown-type storage capacitor 16 isfabricated using container technology. However, it should be evidentthat the type of storage device used and method of fabricating thedevice may be varied. The present embodiment of the memory cell 12advantageously eliminates leakage current from the capacitor 16 to thesubstrate 32 since the capacitor 16 is completely isolated from thesubstrate except through the source 20. Thus, when the access FET 14 isoff, there is no p-n leakage path from the storage device (capacitor 16)to the substrate 32 as with conventional designs.

One technique for fabricating a container cell to be used as the storagecapacitor 16 is by disposing a sacrificial oxide layer (not shown) ontop of the structure illustrated with reference to FIG. 9. The oxidelayer is disposed at a thickness at least as high as what will later bethe height or vertical thickness of the storage polysilicon layer 50.For instance, the thickness of the sacrificial oxide may beapproximately 2.0 microns. Once the sacrificial oxide is disposed, holesare drilled or etched in the oxide to create wells which are verticalwith respect to the surface of the substrate. After the wells arecreated, the storage polysilicon layer 50 may be disposed in the wells.The storage polysilicon layer 50 is disposed to make contact with the n+contact region 48 of the pillar 33. This interface provides theconnection of the FET 14 to the capacitor 16. Next, the polysiliconlayer 50 is etched using masks and photoresist to create the containerpattern of the polyslicon layer 50 as illustrated in FIG. 10. After thestorage polysilicon layer 50 is disposed and etched, the remainder ofthe sacrificial oxide layer is removed leaving only the crown-shaped orcontainer-shaped structure of the storage polysilicon layer 50. Next, adielectric layer 52 may be disposed over the polysilicon layer 50.Finally, a cell plate conductive layer 54 may be disposed on the topsurface of the dielectric layer 50 to complete the storage device. Theconductive layer 54 may be a polysilicon layer, for example.Alternatively, the conductive layer 54 may be a metal, such as aluminum.As can be appreciated by those skilled in the art, a number offabrication techniques may be used to implement current containertechnology to create the storage capacitors 16. Further, storagecapacitors 16 may comprise a number of other storage devices fabricatedusing conventional techniques outside of container technology.

FIG. 11 illustrates an alternate embodiment of the bitline BL. Morespecifically, FIG. 11 illustrates a cross-sectional top view of analternate embodiment of the structure illustrated with reference to FIG.4 and taken along cut lines 5-5. As can be seen, the polysilicon layer36A is patterned to provide semi-annular rings around the siliconpillars 33. Thus, the polysilicon layer 36A which forms the bitlines ofthe memory array described with reference to FIG. 1 extends to connecteach of the silicon pillars 33 in a single column. As previouslydescribed, the silicon pillar 33 also includes n+ contact regions 38Awhich may be formed by out diffusion from the polysilicon layer 36A.Thus, the present exemplary embodiment provides a polysilicon layer 36Awhich is patterned to surround only a portion of the pillar 33.Advantageously, the alternate exemplary embodiment illustrated withreference to FIG. 11 may provide for further pitch reduction and thus,reduction in the area of each memory cell and overall die size.

Similarly, the wordline WL, may be patterned to provide a semi-annularring. FIGS. 12 and 13 illustrate an alternate embodiment of the wordlineWL, incorporating semi-annular rings. FIG. 12 illustrates an alternativeview of the structure illustrated in FIG. 7. Thus, after deposition ofthe oxide layer 40 and the growth of the gate oxide layer 42, apolysilicon layer is disposed, patterned and etched to form thepolysilicon layer 44A having semi-annular rings. As can be appreciated,the wordline polysilicon layer 44A extends in a direction perpendicularto the page and thus, the view of the structure illustrated in FIG. 12includes the polysilicon layer 44A on only one side of the pillar 33.However, as can be appreciated, the wordline polysilicon layer 44A ispatterned about a portion of the pillar 33, as further illustrated withrespect to FIG. 13.

FIG. 13 illustrates a cross-sectional top view of the alternateembodiment illustrated with reference to FIG. 12 and taken along cutlines 13-13. As can be seen, the wordline polysilicon layer 44A ispatterned to provide semi-annular rings around the silicon pillars 33.The wordline polysilicon layer 44A is patterned such that it runsperpendicular to the bitline polysilicon layer 36. As can beappreciated, the semi-annular wordline polysilicon layer 44A may beimplemented along with the semi-annular bitline polysilicon layer 36Adescribed with reference to FIG. 11. Further, while FIGS. 11-13illustrate semi-annular rings, it should be evident that an annular ringmay extend around any desirable portion (e.g. more than half or lessthan half) of the pillar 33. For instance, it may be advantageous toprovide annular rings that extend around only a quarter to a third ofthe circumference of the pillar 33. Alternatively, it may beadvantageous to provide annular rings that extend around two-thirds tothree-quarters of the circumference of the pillar 33, for example.

FIG. 14 illustrates an alternate embodiment of the structure illustratedin FIG. 9, implementing an alternate technique of fabricating thewordline WL. FIG. 15 illustrates a cross-sectional top view of thealternate embodiment illustrated in FIG. 14 and taken along the cutlines 15-15. In the present exemplary embodiment, the wordlinepolysilicon layer 44 is replaced with a thin gate conductor layer 44Band a thick signal conductor layer 44C. As can be seen, the thin gateconductor layer 44B completely surrounds the pillar 33. The thin gateconductor layer 44B may have a thickness extending from the surface ofthe pillar 33 of less than 0.1 microns, for example. After deposition,patterning and etching of the thin conductor layer 44B, a dielectriclayer 46A may be disposed. Unlike the embodiment illustrated in FIG. 9,however, the dielectric layer 46A is not disposed to cover the entirepillar 33. The dielectric layer 46A is disposed such that a portion ofthe pillar remains uncovered, as illustrated in FIG. 14.

Next, the thick signal conductor layer 44C is disposed, patterned andetched to form the wordline WL. The gate conductor layer 44B iselectrically coupled to the signal conductor layer 44C. In one exemplaryembodiment, the gate conductor layer 44B and the signal conductor layer44C are each polysilicon layers. However, as can be appreciated, thegate conductor layer 44B and the signal conductor layer 44C may bedifferent materials. For instance, the gate conductor layer 44B may be apolysilicon layer, while the signal conductor layer 44C may be atungsten layer. To complete the structure, a dielectric layer 46B may bedisposed to a thickness sufficient to cover the pillars 33, and thesuface of the structure may be planarized, as previously described.Advantageously, by providing a thin gate conductor layer 44B coupled toa thick signal conductor layer 44C, a smaller pitch between structuresmay be implemented, thereby reducing cell size and overall die size.

As can be appreciated, while the present wordline and bitline structuresare described as being fabricated through deposition techniques, otherprocesses, such as a damascene process may implemented to form thewordlines and bitlines in accordance with the present techniques.Further, while the present exemplary embodiments have illustrated theannular gate structures with respect to DRAM memory devices, the presenttechniques may be implemented in a number of other applications, such asflash memory cells, SRAM memory cells, anti-fuse devices, image sensorsand simple logic gates, for example.

FIG. 16 illustrates a schematic diagram of simple logical gate structure60 that may be fabricated in accordance with the present techniques.FIG. 17 illustrates an exemplary structure that may be implemented tofabricate the logical gate structure 60 illustrated in FIG. 16. The gatestructure 60 of FIG. 16 includes a first transistor 62 coupled inparallel with a second transistor 64. Each transistor 62 and 64 has arespective gate terminal 66 and 68. The source terminals of eachtransistor 62 and 64 are coupled to each other at a common node 70 suchthat they may be tied to a common reference SIGNAL1. The drain terminalsof each transistor 62 and 64 are coupled to each other at a common node72, such that they can be tied to a common reference SIGNAL2.

FIG. 17 illustrates the fabrication of the gate structure 60, inaccordance with the techniques previously described above. Thedeposition techniques, exemplary materials and deposition thicknessesdescribed above may be used to supplement the description of the presentexemplary embodiment. For clarity, like reference numerals have beenused to illustrate layers previously described. Accordingly, the gatestructure 60 includes a substrate 32A, such as a p-doped silicon, havinga silicon pillar 33A. An insulation layer, such as an oxide layer 34A,is disposed over the substrate 32A. A conductive layer, such as apolysilicon layer 36B, is disposed over the oxide layer 34A. Thepolysilicon layer 36B may be patterned to form annular rings around thepillar 33A or partial annular rings, such as semi-annular rings, aspreviously described. Because the present exemplary structure is not aDRAM cell, the polysilicon layer 36B does not form a bitline for thegate structure 60. However, the polysilicon layer 36B serves a similarfunction in that it provides a signal path. Accordingly, the polysiliconlayer 36B may be implemented to provide the common reference SIGNAL2that is coupled to the common node 72 of the gate structure 60,illustrated in FIG. 16. A second insulation layer, such as an oxidelayer 40A is disposed over the polysilicon layer 36A. Further, n+contact regions 38A are formed near the base of the pillar 33A. The topof the pillar 33A may include a contact region 48A which may beelectrically coupled to a SIGNAL1 at the common node 70 of the gatestructure 60.

A gate oxide layer 42A may be disposed or grown about the pillar 33A.Because the gate stricture 60 includes two gates 66 and 68, two isolatedconductive layers such as polysilicon layers 44D and 44E are disposed.The polysilicon layers 44D and 44E are electrically isolated withrespect to each other and form the gates 66 and 68 of the gate structure60. As with the polysilicon wordline 44, the polysilicon layers 44D and44E extend in a direction perpendicular to the page. Each polysiliconlayer 44D and 44E may be patterned to form a partial annular ring aboutthe pillar 33A. To provide electrical isolation of the polysiliconlayers 44D and 44E, each of the partial annular rings may extend aroundapproximately one-third of the circumference of the pillar 33A, forexample. FIG. 18 illustrates a cross-sectional top view of the structureillustrated with reference to FIG. 17 and taken along cut lines 18-18after deposition of the dielectric layer 46A. Alternately, thepolysilicon layers 44D and 44E may be electrically isolated by disposingthe polysilicon layers 44D and 44E in different planes along the lengthof the pillar 33A, as can be appreciated by those skilled in the art.

FIG. 19 illustrates a schematic diagram of another logical gatestructure 74 that may be fabricated in accordance with the presenttechniques. FIG. 20 illustrates an exemplary structure that may beimplemented to fabricate the logical gate structure 74 illustrated inFIG. 19. The gate structure 74 of FIG. 20 includes a first transistor 76coupled in parallel with a second transistor 78. Each transistor 76 and78 has a respective gate terminal 80 and 82. The source terminals ofeach transistor 76 and 78 are coupled to each other at a common node 84such that they may be tied to a common reference SIGNAL1. The drainterminals of each transistor 76 and 78 are coupled to each other at acommon node 86. The common node 86 is coupled to the source terminal ofa third transistor 88. The third transistor 88 has a respective gateterminal 90. The drain terminal 92 of the third transistor 88 is coupledto a common reference SIGNAL2.

FIG. 20 illustrates the fabrication of the gate structure 74, inaccordance with the techniques previously described above. The gatestructure 74 includes a substrate 32B, such as a p-doped silicon, havinga silicon pillar 33B. An insulation layer, such as an oxide layer 34B,is disposed over the substrate 32B. A conductive layer, such as apolysilicon layer 36C, is disposed over the oxide layer 34B. Thepolysilicon layer 36C may be patterned to form annular rings around thepillar 33B or partial annular rings, such as semi-annular rings, aspreviously described. The polysilicon layer 36C may be implemented toprovide the common reference SIGNAL2 to the drain terminal of the thirdtransistor 88 of the gate structure 74, illustrated in FIG. 19. A secondinsulation layer, such as an oxide layer 40B is disposed over thepolysilicon layer 36C. Further, n+ contact regions 38B are formed nearthe base of the pillar 33B. The top of the pillar 33B may include acontact region 48B that may be electrically coupled to a referenceSIGNAL1 at the common node 84 of the gate structure 74.

A gate oxide layer 42B may be disposed or grown about the pillar 33B. Apolysilicon layer 44F is disposed to form the gate 90 of the transistor88. The polysilicon layer 44F extends in a direction perpendicular tothe page and may be patterned to form an annular ring completely aboutthe pillar 33B or about a portion of the pillar 33B, as previouslydescribed. Next, an insulating material such as an oxide layer 94 may bedisposed to isolate the gate 90 of the transistor 88 from the gates 80and 82 of transistors 76 and 78 (FIG. 19).

Next, two isolated polysilicon layers 44G and 44H are disposed to formthe gates 80 and 82 of the transistors 76 and 78. The polysilicon layers44G and 44H are electrically isolated with respect to each other andform the gates 76 and 78 of the gate structure 74. As with thepolysilicon layers 44D and 44E illustrated with reference to FIGS. 17and 18, the polysilicon layers 44G and 44H extend in a directionperpendicular to the page and are patterned to form partial annularrings about the pillar 33B. To provide electrical isolation of thepolysilicon layers 44G and 44H, each of the partial annular rings mayextend around approximately one-third of the circumference of the pillar33B, for example.

While the invention may be susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and have been described in detail herein.However, it should be understood that the invention is not intended tobe limited to the particular forms disclosed. Rather, the invention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the followingappended claims.

1. An integrated circuit device comprising: a substrate; a pillar of semiconductor material extending from the substrate surface and having a first doped region formed in the semiconductor material at a first end of the pillar and having a second doped region formed in the semiconductor material at a second end of the pillar, wherein the second end of the pillar is more proximate to the substrate surface than the first end; and a first annular ring disposed about at least a portion of the pillar, wherein the first annular ring comprises a conductive material.
 2. The integrated circuit device, as set forth in claim 1, wherein the pillar comprises silicon.
 3. The integrated circuit device, as set forth in claim 1, wherein the pillar comprises a circular cross-section.
 4. The integrated circuit device, as set forth in claim 1, wherein the pillar comprises a square-shaped cross-section.
 5. The integrated circuit device, as set forth in claim 1, wherein the pillar extends in a direction approximately perpendicular to the substrate surface.
 6. The integrated circuit device, as set forth in claim 1, wherein the first annular ring comprises polycrystalline silicon.
 7. The integrated circuit device, as set forth in claim 1, wherein the pillar is configured to form the channel of a transistor and wherein the first doped region is configured to form one of the drain and source of the transistor and wherein the second doped region is configured to form the other of the drain and source of the transistor.
 8. The integrated circuit device, as set forth in claim 7, wherein the first annular ring is configured to form the gate of the transistor and further configured to induce conduction through the pillar between the first doped region and the second doped region when a voltage is applied to the first annular ring.
 9. The integrated circuit device, as set forth in claim 8, wherein the first annular ring is coupled to a wordline of a memory array.
 10. The integrated circuit device, as set forth in claim 1, wherein the first annular ring is disposed about the pillar forming a continuous ring thereabout.
 11. The integrated circuit device, as set forth in claim 1, wherein the first annular ring is disposed about approximately half of the pillar forming a semi-annular ring thereabout.
 12. The integrated circuit device, as set forth in claim 1, wherein the first annular ring comprises a polycrystalline material.
 13. The integrated circuit device, as set forth in claim 8, comprising a second annular ring disposed about at least a portion of the pillar, wherein the second annular ring is electrically isolated from the first annular ring, and wherein the second annular ring comprises a conductive material.
 14. The integrated circuit device, as set forth in claim 13, wherein the second annular ring is more proximate to the substrate surface than the first annular ring.
 15. The integrated circuit device, as set forth in claim 13, wherein the second annular ring is disposed directly adjacent to the second doped region.
 16. The integrated circuit device, as set forth in claim 13, wherein an oxide layer is coupled between the first annular ring and the second annular ring.
 17. The integrated circuit device, as set forth in claim 13, wherein the second annular ring is coupled to a bitline of a memory array.
 18. The integrated circuit device, as set forth in claim 13, wherein the second annular ring is disposed about the pillar forming a continuous ring thereabout.
 19. The integrated circuit device, as set forth in claim 13, wherein the second annular ring is disposed about approximately half of the pillar forming a semi-annular ring thereabout.
 20. The integrated circuit device, as set forth in claim 8, comprising a storage device coupled to the first doped region of the column. 21-62. (canceled) 